Computer systems, such as personal computers (PCs), typically include a number of individual components, such as a microprocessor, memory modules, various system and bus control units, and a wide variety of data input/output (I/O) and data storage devices. Advances in computer design have brought increased speed and capability to computer systems, while largely maintaining backwards compatibility with devices having less than state-of-the-art technology. The attempt to increase computer system capability and maintain backwards compatibility is evident upon inspection of today's most typical PC designs.
FIG. 1 depicts a typical personal computer system 20. A central processing unit (CPU) 22, such as the Intel.RTM. Pentium.RTM. microprocessor, is connected to a CPU bus 24 which carries address, data and control signals. The CPU bus 24 is connected to a system controller 26 and a data path controller 28. Well-known examples of system and data path controllers include the corresponding chips in the PicoPower.RTM. Vesuvius-LS and the Intel.RTM. Triton chipsets. The system controller 26 accesses a main memory 30 via a memory address and control bus 32. Typically, the main memory 30 includes a number of dynamic random access memory (DRAM) modules, such as FPM, EDO, and burst EDO DRAMs manufactured by Micron Technology, Inc. A data portion of the CPU bus 24 is coupled with the main memory 30 by a data and parity bus 34 and the data path controller 28. A cache memory 36 is connected to the CPU bus 24 and provides the CPU 22 with high speed access to a subset of the information stored in the main memory 30. Typically, the cache memory 36 includes static random access memory (SRAM) memory modules, such as those manufactured by Micron Technology, Inc.
The system controller 26 serves as a bridge circuit (sometimes called the north bridge) between the CPU bus 24 and a system bus, such as peripheral component interconnect (PCI) bus 40. One or more of a wide variety of PCI devices 42 are connected to the PCI bus 40. Well-known examples include a VGA controller, a CD-ROM drive circuitry module with SCSI controller, interface circuitry (such as a PCI-PCI bridge controller) coupling another bus system and associated devices to the PCI bus 40, and PCI expansion slots for future accommodation of other PCI devices not selected during the original design of the computer system.
The PCI bus 40 is coupled with an expansion bus, such as industry standard architecture (ISA) bus 44, by a south bridge, such as PCI-ISA bridge 46. One or more of a wide variety of ISA devices 48 are connected to the ISA bus 44. Well-known examples include a floppy disk drive circuitry module with direct memory access (DMA) controller, a keyboard/mouse controller, and ISA expansion slots for future accommodation of other ISA devices not selected during the original design of the computer system.
The multiple bus computer system architecture shown in FIG. 1 allows the CPU 22 to communicate at very high speed with the cache memory 36, while being buffered from the lower speed PCI devices 42 connected to the PCI bus 40, which in turn are buffered from the still slower ISA devices 48 connected to the ISA bus 44. As a general rule, the ISA devices 48 incorporate technology which was used in some of the earliest PC systems (i.e., PC AT and compatible systems), which at that time included only a single bus system connecting various devices to the CPU. The now traditional multiple bus architecture of FIG. 1 accommodates today's high speed CPUs and data I/O and storage devices, while maintaining the backwards compatibility with the older, slower ISA devices 48.
FIG. 2 is a functional block diagram which depicts some of the circuits integrated within the system controller 26 of FIG. 1. CPU interface circuitry 50 interfaces the other components of the system controller 26 with the control and address signals associated with the CPU 22. Similarly, PCI interface circuitry 52 interfaces the other components of the system controller 26 with the control signals and associated protocol of the PCI bus 40. The system controller 26 also includes a main memory controller 54 which accesses the main memory 30, as described above. Similarly, a cache memory controller 56 accesses the cache memory 36. Typically, the system controller 26 also integrates a power management controller 58 and reset and clock interface circuitry 60, whose operation and function is well known in the art.
FIG. 3 is a functional block diagram which depicts some of the circuits integrated within the PCI-ISA bridge 46 of FIG. 1. PCI bus interface and data path circuitry 60 interfaces other components of the PCI-ISA bridge 46 with the control and address/data lines of the PCI bus. Similarly, ISA bus interface and data path circuitry 62 interfaces other components of the PCI-ISA bridge 46 with the control, address, and data lines of the ISA bus 44. The PCI-ISA bridge 46 also includes reset and clock interface circuitry 64, as is well known in the art. Additionally, well-known components oftentimes referred to as "ISA legacy circuits" are included in the PCI-ISA bridge 46. Examples of these ISA legacy circuits include a direct memory access (DMA) controller 66, an interrupt controller 68, and a timer counter unit 70. The DMA controller 66 receives DMA request signals from the ISA devices 48 and controls the block transfer of data between the ISA devices 48 and the main memory 30 (see FIG. 1), as is well known in the art. The interrupt controller 68 receives interrupt request signals from both the PCI devices 42 (via an interrupt router integrated within the PCI-ISA bridge 46) and the ISA devices 48, prioritizes those requests, and notifies the system controller 26 and/or CPU 22 of the needed service, as is well known in the art. The timer counter unit 70 measures time intervals associated with such activities as loud speaker control, time-of-day display, and various system events, as is well known in the art.
As shown in FIG. 1, the system controller 26 and data path controller 28 are each positioned between the CPU bus and PCI bus 40 and each are coupled with the main memory 30. Apparently, the cost and complexity of the computer system 20 could be reduced by integration of these components. Until recently, however, limitations on total pin count per chip made such integration difficult. New chip connection schemes, such as ball grid arrays, allow a higher pin count per chip, and new system controllers, such as the Intel.RTM. 82430HX system controller, now integrate the circuitry and functions of the system controller 26 and the data path controller 28 depicted in FIG. 1.
Improvement of CPUs and of the PCI and other local bus systems continues, with increased speed and system capability improvements. In the not too distant future, the ISA bus and associated devices will likely be eliminated. In the meantime, however, advances in computer system design must still provide for backwards compatibility to the ISA bus and associated devices. Today's computer designer strives for improved computer system performance and cost, but without loss of such backwards compatibility.